The future of printed circuit board technology will be primarily driven by the increasing miniaturization requirements of the applications. This means that component sizes need to be reduced, as do the structure sizes of the conductors and the z-axis interconnects. The current requirements for 60 µm line/space will develop over the next few years to 50 µm line/space and even down to ~30 µm line/space. Existing processes in interconnection technology will have to be optimized in order to fulfill future requirements, but new structuring processes will also have to be investigated.

 

Together with improving resolutions in the exposure processes, improvements in registration accuracy and the etching process are also required.

 

AT&S is examining the potential of the widest possible range of optimization approaches for the various different processes.